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18 - bit, 5 msps pulsar differential adc data sheet ad7960 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its us e. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features throughput: 5 msps 18 - bit resolution with no missing codes excellent ac and dc performance dynamic range: 100 db snr: 99 db thd: ?117 db inl: 0.8 lsb (typical), 2 lsb (maximum) dnl: 0. 5 lsb (typical), 0.99 lsb (maximum) true differential analog input voltage range: 4.096 v or 5 v low power dissipation 46.5 mw at 5 msps with external reference buffer (echo ed clock mode) 6 4.5 mw at 5 msps with inte rnal reference buffer (echo ed clock mode) 39 mw at 5 msps with external reference buffer (self clock ed mode , cnv in cmos mode ) sar architecture no latency/pipeline delay external r eference o ptions : 2 .048 v buffered to 4.096 v ( i nternal r eference buffer) , 4.096 v , and 5 v serial lvds interface self c lock ed m ode echoed c lock m ode lvds or cmos option for conversion control (cnv signal) operating temperature range of ?40c to +85c 32 - lead , 5mm 5mm lfcsp (qfn) applications digital imaging s ystems digital x - ray s computed t omography ir c ameras mri g radient c ontrol high s peed d ata a cquisition spectroscopy test e quipment functional block dia gram figure 1. general description the ad7960 is an 18 - bit, 5 ms ps , charge redistribution succes sive approximation (sar), analog - to - digital converter (adc). the sar architecture allows unmatched performance both in noise and in linearity . the ad7960 contains a low power, high speed, 18- bit sampling adc, an internal conversion clock , and an internal reference buffer. on the cnv edge, t he ad7960 samples the voltage difference between the in+ and in? pins. the voltages on these pins swing in opposite phase between 0 v and 4.096 v and b etween 0 v and 5 v. the reference voltage is applied to the part externally. all conversion results are available on a single lvds self clocked or echo ed clock serial interface. the ad7960 is available in a 32 - lead lfcsp (qfn) with operation specified from ?40c to +85c. table 1 . fast pulsar? adc selection input type 1 msps to <2 msps 2 msps to 3 msps 5 msps to 6 msps 10 msps differential , 1 16- bit AD7653 ad7985 ad7667 ad7980 ad7983 true bipolar, 16- bit ad7671 differential , 2 16- bit ad7677 ad7621 ad7625 ad7626 ad7623 ad7622 ad7961 differential , 2 18- bit ad7643 ad7641 ad7960 ad7982 ad7986 ad7984 1 ground s ense . 2 antiphase . ad7960 clock logic serial lvds in? in+ refin ref vcm sar 2 cn v+, cn v? en0 d+, d? dc o+, dc o? clk+, clk? cap dac vdd1 vdd2 vio en1 en2 en3 gnd 09659-001
ad7960 data sheet rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 7 ther mal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 13 theory of operation ...................................................................... 14 circuit information .................................................................... 14 converter information .............................................................. 14 transfer function ....................................................................... 15 analog inp uts .............................................................................. 15 typical applications ................................................................... 16 voltage reference options ........................................................ 17 power supply ............................................................................... 18 digital interface .............................................................................. 19 conversion control ................................................................... 19 applications information .............................................................. 22 layout .......................................................................................... 22 evaluating ad7960 performance ............................................. 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 8/13 revis ion 0: initial version
data sheet ad7960 rev. 0 | page 3 of 24 specifications vdd1 = 5 v; vdd2 = 1.8 v; vio = 1.8 v; ref = 4.096 v; all specifications t min to t max , unless otherwise noted. table 2. parameter test conditions/comments min typ max unit resolution 18 bits analog input voltage range v in+ ? v in? ?v ref +v ref v operating input voltage v in+ , v in? to gnd ?0.1 v ref + 0.1 v common - mode input range 1 v ref /2 ? 0.05 v ref /2 v ref /2 + 0.05 v cmrr f in = 500 khz 70 db input leakage current acquisition phase 60 na throughput complete cycle 200 ns throughput rate 0 5 msps dc accuracy no missing codes 18 bits integral linearity error ?2 0. 8 +2 lsb differential linearity error ?0.99 0. 5 + 0.99 lsb transition noise 1 .1 lsb zero error ?6 +6 lsb zero error drift 1 ? 0.2 5 0.01 +0.2 5 p pm/c gain erro r ?3 0 5 +30 lsb gain error drift 1 ? 0.5 0. 05 +0.5 ppm/c power supply sensitivity 2 vdd1 = 5 v 5% 1 lsb vdd2 = 1.8 v 5% 2 lsb ac accuracy f in = 1 khz, ?0.5 dbfs, v ref = 5 v dynamic range 98 100 db signal - to - noise ratio 97 99 db spurious - free dynamic range 119 db total harmonic distortion ?117 db signal - to - noise - and - distortion ratio 96.5 98.5 db f in = 1 khz, ?0.5 dbfs, v ref = 4.096 v dynamic range 97 98.5 db signal - to - noise ratio 95 97 db spurious - free dynamic range 115 db total harmonic distortion ?11 3 db signal - to - noise - and - distortion ratio 94.5 9 6.5 db ?3 db input bandwidth 3 en2 = 0 28 mhz reference buffer refin input voltage range 1 2.042 2.048 2.054 v ref output voltage range ref at 25c, en 3 to en 0 = xx01 or xx10 4.08 6 4.096 4.10 6 v line regulation vdd1 = 5 v 5%, vdd2 = 1.8 v 5% 20 v gain drift 1 ? 25 4 + 25 ppm/c external reference voltage range refin pin, en 1 to en0 = 01 2.048 v ref pin, en1 to en 0 = 10 4 4.096 v ref pin, en1 to en 0 = 01 4 5 v current drain 5 msps, ref = 4.096 v 1.0 5 1.11 ma 5 msps, ref = 5 v 1.36 1.43 ma
ad7960 data sheet rev. 0 | page 4 of 24 parameter test conditions/comments min typ max unit vcm pin vcm output ref/2 vcm error ?0.01 +0.01 v output impedance 5 .1 k lvds i/o (ansi -644) data format serial lvds twos complement differential output voltage, v od r l = 100 245 290 454 mv c ommon - mode output voltage, v ocm r l = 100 980 5 1130 1375 mv differential input voltage, v id 100 650 mv common - mode input voltage, v icm 800 1575 mv power supplies specified performance vdd1 4.75 5 5.25 v vdd2 1.71 1.8 1.89 v vio 1.71 1.8 1.89 v operating currents 6 static not converting, internal reference buffer disabled self clocked mode, cnv in cmos mode 7 vdd1 8 40 a vdd2 8 70 a vio 5 5. 3 ma static not converting, internal reference buffer enabled self clocked mode, cnv in cmos mode 7 vdd1 2. 6 2. 9 ma vdd2 9 72 a vio 4. 4 5. 3 ma converting: internal reference buffer disabled echoed clock mode, cnv in lvds mode vdd1 2 2. 2 ma vdd2 11. 4 13.5 ma vio 9 10. 3 ma converting: internal reference buffer enabled echoed clock mode, cnv in lvds mode vdd1 5. 6 6 ma vdd2 11. 4 13.5 ma vio 9 10. 3 ma converting: internal reference buffer disabled self clocked mode, cnv in cmos mode 7 vdd1 2 2.2 ma vdd2 11.4 13.5 ma vio 4.9 5.6 ma snooze mode vdd1 2 4.1 a vdd2 1 40.3 a vio 0.1 4.8 a power - down en 3 to en 0 = x000 vdd1 1 2.8 a vdd2 1 37.8 a vio 0.2 4.6 a power dissipation static not converting , internal reference buffer disabled self clocked mode, cnv in cmos mode 7 9 10.3 mw static not converting, internal reference buffer enabled self clocked mode, cnv in cmos mode 7 21 25 mw
data sheet ad7960 rev. 0 | page 5 of 24 parameter test conditions/comments min typ max unit converting: internal reference buffer disabled echoed clock mode, cnv in lvds mode 46.5 56.2 mw converting: internal reference buffer enabled echoed clock mode, cnv in lvds mode 64.5 76.4 mw converting: internal reference buffer disabled self clocked mode, cnv in cmos mode 7 39 47.4 mw power - down en 3 to en 0 = x000 7.2 94.5 w energy per conversion self c locked, cnv in cmos m ode 7 7.8 9.5 nj/sample temperature range specified performance t min to t max ?40 +85 c 1 the minimum and maximum values are guaranteed by characterization. 2 using an external reference. 3 see table 8 for logic levels of enable pins. when en2 = 1, the ?3 db input bandwidth is 9 mhz. use this lower bandwidth only when the throughput rate is 2 msps or lower. 4 the refin pin is tied to 0 v in this mode. 5 the ansi - 644 lvds specification has a minimum common - mode output (v ocm ) of 1125 mv. 6 the current dissipated in the v cm circuitry when enabled is ref/2 0 k an d is not included in the operating currents listed. 7 cnv+ works as a cmos input when cnv? is grounded. see table 6 for additional information. timing specification s vdd1 = 5 v; vdd2 = 1.8 v; vio = 1.71 v to 1.89 v; ref = 5 v or 4.096 v; all specifications t min to t max , unless otherwise noted. table 3. parameter symbol min typ max unit time between conversions t cyc 200 ns acquisition time t acq t cyc ? 100 ns cnv high time t cnvh 10 0.6 t cyc ns cnv to d (msb) ready t msb 200 ns cnv to last clk (lsb) delay t clkl 1 60 ns clk period 1 t clk 3.33 4 (t cyc ? t msb + t clkl )/n ns clk frequency f clk 250 300 mhz clk to dco delay (echoed clock mode) t dco 0 3 5 ns dco to d delay (echoed clock mode) t d 0 1 ns clk to d delay t clkd 0 3 5 ns 1 for the maximum clk period, the window available to read data is t cyc ? t msb + t c lkl . divide this time by the number of bits (n) to be read, giving the maximum clk frequency that can be used for a given conversion cnv frequency. in echoed clock interface mode, n = 18; in self clocked int erface mode, n = 20.
ad7960 data sheet rev. 0 | page 6 of 24 timing diagrams figure 2 . echoed clock interface mode timing diagram figure 3 . self clocked interface mode timing diagram clk+ t cyc t acq 1817 cnv+ 1 1817 2 1 2 3 t cnvh t clkl dc o+ 1817 1 1817 2 1 2 3 d+ sample n sample n + 1 d? d17 n d16 n d1 n cl k? cnv? dc o? d0 n ? 1 ac quisit io n ac quisit io n t dco t d t clk 0 t msb d1 n ? 1 d17 n + 1 d16 n + 1 d0 n 0 d15 n + 1 t clkd ac quisit io n 09659-002 clk+ 2019 1 4 2 1 2 3 t acq d+ d? clk? d0 n ? 1 d1 n ? 1 acquisition acquisition t clkd t clk t msb 2019 3 d17 n d16 n d1 n 0 0 1 d0 n d17 n + 1 0 0 1 t cyc cn v+ t cnvh sample n sample n + 1 c nv? acquisition t clkl 09659-003
data sheet ad7960 rev. 0 | page 7 of 24 absolute maximum rat ings table 4. parameter rating analog inputs/outputs in+, in? to gnd ?0.3 v to ref + 0.3 v or 130 ma ref 1 to gnd ?0.3 v to +6 v vcm to gnd ?0.3 v to +6 v refin to gnd ?0.3 v to +6 v supply voltage s vdd1 ?0.3 v to +6 v vdd2, vio ?0.3 v to +2.1 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v input current to any pin except supplies 10 ma operating temperature range (commercial) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c esd h uman b ody model 4 kv machine model 200 v f ield -i nduced c harged - d evice m odel 1.25 kv 1 transient currents of up to 100 ma do not cause scr latch - up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other condi tions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditio ns, that is, a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type ja jc unit 32 - lead lfcsp_vq 40 4 c/w esd caution
ad7960 data sheet rev. 0 | page 8 of 24 pin configuration and function descriptions figure 4 . pin configuration table 6 . pin function descriptions pin no. mnemonic type 1 description 1, 19, 20 vdd1 p analog 5 v supply. decouple the 5 v supply with a 100 nf capacitor. 2, 18, 25 vdd2 p analog 1.8 v supply. decouple this pin with a 100 nf capacitor. 12 vio p input/output interface supply. use a 1.8 v supply and decouple this pin with a 100 nf capacitor. 13, 24 gnd p ground. 26, 27, 28 ref_gnd p reference ground. connect the capacitors on the ref pin between ref and ref_gnd. tie ref_gnd to gnd. 3 refin ai prebuffer reference voltage. it is driven with an external reference voltage of 2.048 v. when driving an external 2.048 v reference, a 100 nf capacitor is required. if using an external 5 v or 4.096 v reference (connected to ref), connect this pin to ground. 4, 5, 6, 7 en0, en1, en 2, 2 en3 di enable. 2 the logic levels of these pins set the operation of the device , as described i n table 8 . 8, 9 cnv?, cnv+ di convert input. these pins act as the conversion control pin. on the rising edge of these pins, the analog inputs are sampled and a conversion cycle is initiated. cnv+ works as a cmos input when cnv? is grounded; otherwise, cnv+ and cnv? are differential lvds inputs. 10, 11 d?, d+ do lvds data outputs. the conversion data is output serially on these pins. 14, 15 dco?, dco+ do lvds buffered clock outputs. when dco+ is g rounded, the self clocked interface mode is selected. in this mode, the 18 - bit results o n d are preceded by an initial 0 (which is output at the end of the previous conversion), followed by a 2 - bit header ( 10 ) to allow synchronization of the data by the d igital host with extra logic. the 1 in this header provides the reference to acquire the subsequent conversion result correctly. when dco+ is not grounded, the echoed clock interface mode is selected. in this mode, dco is a copy of clk. the data bits are output on the falling edge of dco+ and can be captured in the digital host on the next rising edge of dco+. 16, 17 clk?, clk+ di lvds clock inputs. this clock shifts out the conversion results on the falling edge of clk+. 21 vcm ao common - mode output. when using any reference scheme, this pin produces one - half the voltage present on the ref pin, which can be useful for driving the common mode of the input amplifiers. 22 in? ai differential negative analog input. re ferenced to and must be driven 180 out of phase with in+. 23 in+ ai differential positive analog input. referenced to and must be driven 180 out of phase with in?. 29, 30, 31, 32 ref ai/o buffered reference voltage. when using the 2.048 v external reference (refin input), the 4.096 v system reference is produced at this pin. when using an external reference of 4.096 v or 5 v on this pin , the internal reference buffer must be disabled. connect the ref pins with the shortest trace possible to a single 10 f, low esr, low esl capacitor. the other side of the capacitor must be placed close to gnd. 33 ep exposed pad. the exposed pad is located on the underside of the package. connect the exposed pad to the ground plane of the pcb using multiple vias. 1 ai = analog input; ai/o = bidirectional analog; ao = analog output; di = digital input; do = digital output; p = power. 2 en2 = 0 sets the 28 mhz of input bandwidth, and en2 = 1 sets the 9 mhz of input bandwidth. en3 = 1 enables the v cm reference output. pin 1 indicator 1v dd 1 2v dd 2 3refin 4en0 5en1 6en2 7en3 8c nv? 24 gnd 23 in+ 22 in? 21 vcm 20 v dd 1 19 v dd 1 18 v dd 2 17 clk+ 9 cn v+ 10 d? 1 11 d+ 12 vio 13 gnd 14 dc o? 15 dc o+ 16 clk? 32 r ef 31 r ef 30 r ef 29 r ef 28 ref_gnd 27 ref_gnd 26 ref_gnd 25 v dd 2 top view (not to s ca le) ad7960 09659-004 notes 1. connect the exposed pad to the ground plane of the pcb using multiple vias.
data sheet ad7960 rev. 0 | page 9 of 24 typical performance characteristics vdd1 = 5 v; vdd2 = 1.8 v; vio = 1.8 v; all specifications t = 25c, unless otherwise noted. figure 5 . integral nonlinearity vs. code and temperature, ref = 5 v figure 6 . integral nonlinearity vs. code and temperature, ref = 4.096 v figure 7. histogram of dc input at code center, ref = 5 v figure 8. differential nonlinearity vs. code and temperature, ref = 5 v figure 9 . differential nonlinearity vs. code and temperature, ref = 4.096 v figure 10 . histogram of dc input at code transition, ref = 5 v code ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 0 50000 100000 150000 200000 250000 in l (lsb) ?40c +25c +85c 09659-101 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 0 50000 100000 150000 200000 250000 in l (lsb) code ?40c +25c +85c 09659-102 203 5909 59315 263386 574212 731453 299523 76526 8878 464 6 0 200000 400000 600000 800000 66db 66dc 66dd 66de 66df 66e0 66e1 66e2 66e3 66e4 66e5 66e6 count code (hex) 601563 09659-109 ?0.50 ?0.25 0 0.25 0.50 0 50000 100000 150000 200000 250000 dn l (lsb) code 09659-104 ?40c +25c +85c code ?0.50 ?0.25 0.25 0.50 0 50000 100000 150000 200000 250000 dn l (lsb) 09659-105 ?40c +25c +85c 0 200000 400000 600000 800000 66db 66dc 66dd 66de 66df 66e0 66e1 66e2 66e3 66e4 66e5 66e7 66e6 count 29 1254 2213 64 1 code (hex) 20298 137500 417791 167625 29231 460940 682452 702042 09659-112
ad7960 data sheet rev. 0 | page 10 of 24 figure 11 . histogram of dc input at code center, ref = 4.096 v figure 12 . 20 khz, ?0.5 db fs input tone fft, wide view , ref = 5 v figure 13 . 20 khz, ?0.5 dbfs input tone fft, zoomed view, ref = 5 v figure 14 . histogram of dc input at code transition, ref = 4.096 v figure 15 . 20 khz, ?0.5 dbfs input tone fft, wide frequency view , ref = 4.096 v figure 16 . 20 khz, ?0.5 dbfs input tone fft, zoomed view , ref = 4.096 v 0 7 277 3389 206 8 0 843b 843c 843d 843e 843f 8440 8441 8442 8443 8444 8445 8446 8447 8448 8449 844a 844b 0 200000 400000 600000 800000 count code (hex) 29567 3934 126798 322696 318090 122502 27625 524601 529433 612307 09659-113 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500 1000 1500 2000 2500 amplitude (db) frequenc y (khz) input frequency = 20khz snr = 99.8db sinad = 99.7db thd = ?115.9db sfdr = 118.3db 09659-103 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (db) 0 10 20 30 40 50 60 70 80 90 100 input frequency = 20khz snr = 99.8db sinad = 99.7db thd = ?115.9db sfdr = 118.3db frequenc y (khz) 09659-107 843b 843c 843d 843e 843f 8440 8441 8442 8443 8444 8445 8446 8447 8448 8449 844a 844b 0 1 96 513 22 1 0 200000 400000 600000 800000 count code (hex) 16272 1758 83201 251602 47010 6982 176972 393411 573335 600723 469541 09659-116 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500 1000 1500 2000 2500 amplitude (db) frequenc y (khz) input frequency = 20khz snr = 98.4db sinad = 98.3db thd = ?113.6db sfdr = 116.1db 09659-106 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (db) 0 10 20 30 40 50 60 70 80 90 100 input frequency = 20khz snr = 98.4db sinad = 98.3db thd = ?113.6db sfdr = 116.1db frequenc y (khz) 09659-110
data sheet ad7960 rev. 0 | page 11 of 24 figure 17 . 20 khz, ?6 dbfs input tone fft, wide view , ref = 5 v figure 18 . 20 khz, ?6 dbfs input tone fft, wide view , ref = 4.096 v figure 19 . snr and thd vs. frequency, ?6 dbfs , ref = 5 v figure 20 . snr and sinad vs. temperature , ref = 5 v figure 21 . thd vs. temperature, ref = 5 v figure 22 . sfdr vs. temperature, ref = 5 v ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500 1000 1500 2000 2500 amplitude (db) input frequency = 20khz snr = 100.1db sinad = 100.0db thd = ?123.4db sfdr = 120.8db frequenc y (khz) 09659-108 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500 1000 1500 2000 2500 amplitude (db) input frequency = 20khz snr = 98.7db sinad = 98.6db thd = ?121.7db sfdr = 119.5db frequenc y (khz) 09659-111 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 96 97 98 99 100 1 10 100 thd (db) snr (db) frequency (khz) snr thd 09659-117 97.0 97.5 98.0 98.5 99.0 99.5 100.0 ?40 ?20 tempera ture (c) 0 20 40 60 80 snr, sinad (db) 09659-115 snr sinad ?122 ?120 ?1 18 ?1 16 ?1 14 ?1 12 ?1 10 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 thd (db) tempera ture (c) 09659-129 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 tempera ture (c) 1 12 1 14 1 16 1 18 120 122 124 126 sfdr (db) 09659-130
ad7960 data sheet rev. 0 | page 12 of 24 figure 23 . zero error and gain error vs. temperature , ref = 5 v figure 24 . input current (in+, in?) vs. differential input voltage, ref = 5 v figure 25 . supply current vs. temperature, ref = 5 v, self clocked mode, cnv in cmos mode, internal reference buffer disabled figure 26 . power - down current vs. temperature , ref = 5 v figure 27 . supply current vs. throughput, self clocked mode, cnv i n cmos mode , internal reference buffer disabled 0 0.5 1.0 1.5 2.0 2.5 ?40 ?20 0 20 40 60 80 100 zero error and gain error (lsb) temperature (c) zero error gain error 09659-121 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 input current (ma) differentia l input vo lt age (v) in+ in? 09659-125 09659-120 0 2 4 6 8 10 12 14 ?40 ?20 0 20 40 60 80 supply current (ma) tempera ture (c) vdd1 vdd2 vio 0 2 4 6 8 10 ?40 ?20 0 20 40 60 80 current (a) tempera ture (c) vdd2 vdd1 vio 09659-123 09659-126 0 2 4 6 8 10 12 supply current (ma) vdd1 vdd2 vio 0 1 2 3 4 5 throughput (mhz)
data sheet ad7960 rev. 0 | page 13 of 24 terminology differential nonlinearity (dnl) error in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. integral nonlinearity (inl) error linearity error refers to the deviation of each individual c ode from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is meas - ured from the middle of each code to the true straight line. dynamic range dynamic range is the ratio of the rms value of the full scale to the rms noise measured for an input typically at ?60 db. the value for dynamic range is expressed in decibe ls. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad and is expressed in bits by enob = [( sinad db ? 1.76)/6.02] gain error the first transition (from 100 000 to 100 001) should occur at a level ? lsb above nominal negative full scale (?4.0959844 v for the 4.09 6 v range). the last transition (from 011 110 to 011 111) occur s for an analog voltage 1? lsb below the nominal full scale (+4.09595 3 v for the 4.096 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. gain error drift the ratio of the gain error change due to a temperature cha nge of 1c and the full - scale range (2 n ). it is expressed in parts per million. least significant bit (lsb) the least significant bit, or lsb, is the smallest increment that can be represented by a converter. for a fully differential input adc with n bits of resolution, the lsb expressed in volts is n inp-p v lsb 2 (v) = power supply rejection ratio (psrr) var iations in power supply affect the full - scale transition but not the linearity of the converter. psrr is the maximum change in the full - scale transition point due to a change in power supply voltage from the nominal value. signal -to - noise ratio (snr) snr i s the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - noise - and - distortion (sinad) ratio sina d is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. spurious - free dynamic range (sfdr) s fdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal (including harmonics). total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. zero error zero error is the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. zero error drift the ratio of the zero error change d ue to a temperature change of 1c and the full - scale code range (2 n ). it is expressed in parts per million.
ad7960 data sheet rev. 0 | page 14 of 24 theory of operation figure 28 . adc simplified schematic circuit information the ad7960 is a 5 msps , high precision, power efficient, 18 - bit adc that uses sar - based architect ure to provide performance of 99 db snr, 0.8 lsb inl, and 0. 5 lsb dnl. the ad7960 does not exhibit any pipeline delay or latency, making it ideal for multiplexed channel applications. the ad7960 is capable of converting 5,000,000 samples per second ( 5 msps ). the device typically consumes 46.5 mw of power. the ad7960 offers the added functionality of an on - chip reference buffer. if the internal reference buffer is enabled, the ad7960 consume s approximately an additional 1 8 mw of power. the ad7960 is specified for use with 5 v and 1.8 v supplies (vdd1, vdd2). the interface from the digital host to the ad7960 uses 1.8 v logic only. the ad7960 uses an lvds interface to transfer data conversions. the cnv+ and cnv? inputs to the part activate the conversion of the analog input. the cnv+ and cnv? pins can be applied using a cmos or lvds source. the ad7960 is housed in a space - saving, 32 - lead, 5 mm 5 mm lfcsp package. converter informatio n the ad7960 is a 5 msps adc that uses sar - based archi - tecture based on a charge redistribution dac. figure 28 shows a simplified schematic of the adc. th e capacitive dac consists of two identical arrays of 18 binary weighted capacitors that are connected to the two comparator inputs. during the acquisition phase, the terminals of the array tied to the input of the comparator are connected to gnd via sw+ a nd sw?. all independent switches are connected to the analog inputs. in this way, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. a conversion phase is initiated when the acquisition phase is co mplete and the cnv input goes high. note that the ad7960 can receive a cmos or lvds format cnv signal. when the conversion phase begins, sw+ and sw? are opened first. the two - capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs (in+ and in?) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref (the reference voltage), the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 v ref /262,144). the control lo gic toggles these switches, msb first, to bring the comparator back into a balanced condition. at the completion of this process, the control logic generates the adc output code. the ad7960 digital interface uses low voltage differential signaling (lvds) to enable high data transfer rates. the ad7960 conversion result is available for reading after t msb (time from the conversion start until msb is available) elapse s . the user must apply a burst lvds clk signal to the ad7960 to transfer data to the digital host. the clk signal outputs the adc conversion result onto the data output , d. the bursting of the clk signal , illustrated in figure 35 and figure 36, is characterized as follows: ? hold t he differential voltage on clk in a steady state in the window of time between t clkl and t msb . ? the ad7960 has two data read modes. for more information about the echoed clock and self clocked interface modes, see the digital interface section. sw+ comp sw? in+ ref gnd lsb msb 131,072c 65,536c 4c 2c c c cnv+, cnv? in? 131,072c 65,536c 4c 2c c c lsb msb gnd gnd lvds interface output code switches control clk+, clk? dco+, dco? d+, d? data transfer conversion control control logic 09659-0 11
data sheet ad7960 rev. 0 | page 15 of 24 transfer function the ad7960 uses a 5 v or a 4.096 v reference. the ad7960 converts the differential voltage of the antiphase analog i nputs (in+ an d in?) into a digital output. in+ and in? require a ref/2 v common - mode voltage. the 18 - bit conversion result is in msb first, twos complement format. the ideal transfer functions for the ad7960 are shown in figure 29 and table 7 . figure 29 . adc ideal transfer functions (fsr = full - scale range) analog inputs the analog inputs applied to the ad7960 , in+ and in?, must be 180 out of phase with each other. figure 30 shows an equivalent circuit of the input structure of the ad7960 . the two diodes provi de esd protection for in+ and in?. care must be taken to ensure that the analog input signals do not exceed the supply rails of the ad7960 by more than 0.3 v (vdd1 and gnd). if the analog input signals exceed this level, the diodes become forward - biased and start conducting current. these diodes can handle a forward - biased current of 130 ma maximum. however, if the supplies of the input buffer amplifier are different from the vdd1/gnd supply, the analog input signal may eventually exceed the supply rails by more than 0.3 v. in such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the part. figure 30 . equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differ - ential inputs, signals common to both inputs are rejected. the ad7960 shows some degradation in thd with higher analog input frequencies. figure 31 . analog input cmrr vs. frequency table 7 . output codes and ideal input voltages description analog input (in+ ? in?), ref = 5 v analog input (in+ ? in?) , ref = 4.096 v digital output code , twos complement (hex) fsr ? 1 lsb +4.999962 v +4.095969 v 0x1ffff midscale + 1 lsb +38.15 v +31.25 v 0x00001 midscale 0 v 0 v 0x00000 midscale ? 1 lsb ?38.15 v ?31.25 v 0x3ffff ?fsr + 1 lsb ?4.999962 v ?4.095969 v 0x20001 ?fsr ? 5 v ?4.096 v 0x20000 10 0 .. . 0 00 10 0 .. . 0 01 10 0 .. . 0 10 01 1 .. . 1 01 01 1 .. . 1 10 01 1 .. . 1 11 adc code (twos complement) anal og input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb 09659-012 185? 26pf vdd1 in+ or in? 09659-013 0 10 20 30 40 50 60 70 80 90 100 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) 09659-127
ad7960 data sheet rev. 0 | page 16 of 24 typical applications figure 32 shows an example of a typical connection diagram for driving the ad7960 using the two single-ended ada4899-1 devices. the alternative adc drivers are two single-ended ada4897-1 op amps or a differential amplifier ada4932-1 that can drive the inputs of the ad7960 . the ad7960 is an ideal fit for high speed multiplexed applica- tions such as digital x-ray, computed tomography, and infrared cameras that require superior performance in terms of noise, power, and throughput, which significantly reduces cost in these types of applications. the ad7960 has a quiet time requirement of 90 ns to 110 ns during the conversion, where the switching of multiplexer inputs (channels) must not occur to avoid the corruption of conversion. in other words, a delay of less than 90 ns and greater than 110 ns from the cnv rising edge to the multiplexer inputs switching event results in no corruption. if the analog inputs are multiplexed during this quiet conversion time, the current conversion may be corrupted by up to 15 lsbs. if the analog inputs are multiplexed early enough, the inputs can slew fast enough to a full-scale signal and settle the input within the allowed time. the ad7960 offers extremely low noise floor relative to its full- scale input. the combination of high throughput rate, low noise floor, and linearity also makes this part suitable for over- sampling applications such as spectroscopy, mri gradient control, and gas chromatography. the wide dynamic range of the ad7960 allows accurate measurements of both small and large signals from multiple channels. figure 32. typical application diagram 56pf 20 ? ?v s +v s 56pf 20 ? ?v s +v s gnd in+ in? ad7960 vcm ?v s +v s 2.5v ad8031 0.1f 100 ? 100 ? 100 ? 100 ? ref 1 refin vdd1 vdd2 vio cnv clk d dco 10f 2 0.1f 0.1f 0.1f +5v +1.8v +1.8v adr4550 +7v 0v to 5 v vcm = 2.5v 0v to 5 v vcm = 2.5v +5v 0.1f 0.1f +v s ?v s ad8031 0.1f 0.1f 1 see the voltage reference options section. connection to external reference signals is dependent on the en1 and en0 settings. 2 a 10f capacitor with low esl and esr is usually connected between the ref pin and ref_gnd. connect ref_gnd to the common ground of the board. the ref and refin pins are decoupled regardl ess of en1 and en0 settings. 3 buffered vcm pin output gives the required 2.5v common-mode supply for analog inputs. digital interface signals digital host lvds transmit and receive ada4899-1 ada4899-1 vcm 3 09659-015
data sheet ad7960 rev. 0 | page 17 of 24 table 8 . voltage reference options en3 en2 en1 en0 refin reference mode description x 1 0 0 0 x 1 power - down mode . everything is power ed down , including the lvds interface. x 1 0 0 1 0 v interface powered up. reference buffer disabled. an e xternal 5 v reference is applied to the ref pin . connect refin to 0 v in this mode. the bandwidth of the input sampling network is set to 28 mhz. x 1 0 0 1 2.048 v internal reference buffer enabled. an e xternal 2.048 v reference applied to refin pin is required. a b uffered 4.096 v reference is available on the ref pin. the bandwidth of the input sampling network is set to 28 mhz. x 1 0 1 0 0 v internal reference buffer disabled. drive t he ref pins with a 4.096 v external reference. connect refin to 0 v in this mode. the bandwidth of the input sampling network is set to 28 mhz. x 1 0 1 1 0 v snooze mode . 2 lvds powers down. the chip is unresponsive to cnv start pulse s. the wake - up time is fast (5 s) when en3 to en 0 are set to xx01 or xx10. ensure that t he cnv start pulse is low when transitioning in and out of this m ode. 0 1 0 0 x 1 test patterns output on lvds. the adc output is not available on the interface. 1 1 0 0 x 1 in valid mode. x 1 1 0 1 0 v reference buffer disabled . drive t he ref pins with a 5 v external reference. the bandwidth of the input sampling network is set to narrow ( 9 mhz). x 1 1 0 1 2.048 v internal reference buffer enabled and driving ref pin to 4.096 v. the bandwidth of the input sampling network is set to narrow ( 9 mhz). x 1 1 1 0 0 v reference buffer disabled. drive t he ref pins with a 4.096 v external reference. the bandwidth of the input sampling network is set to narrow ( 9 mhz). x 1 1 1 1 0 v snooze mode . 2 lvds powers down. the chip is unresponsive to cnv start pulses . the wake - up time is fast (5 s) when en 3 to en 0 are set to xx01 or xx10. 1 x = dont care. 2 the snooze mode is not useful when the internal reference buffer is used because th e fast wake - up is not possible due to the settling of the internal reference buffer. voltage reference op tions the ad7960 allows buffering of the reference voltage. the ad7960 conversions are referred to a 5 v or 4.096 v reference voltage. there are three options for using an external reference . ? externally buffered reference source of 5 v applied to the ref pin. ? ex ternally buffered reference source of 4.096 v applied to the ref pin. ? external reference of 2.048 v applied to the refin pin (high impedance input). the on - chip buffer gains this by 2 and drives the ref pin with 4.096 v. the recommended external reference s for the ad796 0 are the adr4520 / adr4540 / adr4550 and adr440 / adr444 / adr445 . the various options for creating this reference are controlled by the en1 and en0 pins (see table 8 ). the ?3 db input bandwidth is controlled by en2. en2 = 0 sets a ?3 db input bandwidth of 28 mhz , and en2 = 1 sets a ?3 db input bandwidth of 9 mhz . use t his lower bandwidth ( 9 mhz) only when the sample rate is 2 msps or lower. en3 = 1 enables the vcm reference output , and en3 = 0 disables the vcm reference output voltage. the best snr and dynamic range performance is achieved by using the larger 5 v external voltage reference option. the improvement achieved is approximately 1.7 db and is calculated using the following equation: ? ? ? ? ? ? = 0.5 096.4 log20 snr wake- up time from power - down and snooze mode s the ad7960 power s down when en 3 to en 0 = x000 and operates in snooze mode when en 3 to en 0 = xx11 using the correct refer ence choice as shown in table 8 . typical wake - up times for the sele cted reference settings from power - down and s nooze mode are shown in table 9 and table 10 . each wake - up time repr esents the duration from the e n3 to e n0 logic transit ion to when the adc is ready for a cnv rising edge. for example, the user must wait 1.4 ms from power - down before applying cnv pulses to receive data conversion results when using refin = 0 v. table 9 . wake - up time from power - down mode , en 3 to en 0 = x000 to active mode wake - up t ime en 3 to en 0 = xx01, refin = 0 v 1.4 ms en 3 to en 0 = xx01, refin = 2.048 v 8 ms en 3 to en 0 = xx10, refin = 0 v 1.4 ms table 10. wake - up time from snooze mode , en 3 to en 0 = xx11 to active mode wake - up time en 3 to en 0 = xx01, refin = 0 v 5 s en 3 to en 0 = xx01, refin = 2.048 v 8 ms en 3 to en 0 = xx10, refin = 0 v 5 s
ad7960 data sheet rev. 0 | page 18 of 24 power supply the ad7960 uses both 5 v (vdd1) and 1.8 v (vdd2) power supplies, as well as a digital input/output interface supply (vio). drive t he en 3 to en 0 pins with a 1.8 v logic level . vio and vdd2 can be taken from the same 1.8 v source; however, it is best practice to isolate the vio and vdd2 pins using separate traces as well as to decouple each pin separately. the 5 v and 1.8 v supplies required for the ad7960 can be generated using analog devices, inc., ldos such as the adp7104 -5 and the adp124 -1.8 . figure 33 shows the psrr vs . supply f requency of the ad7960 . the ad7960 core powe r scales with throughput as shown in figure 34 , offering significant power budget savings at lower speed operation. figure 33 . psrr vs. supply frequency power - up as is best practice for all adcs, power on the core supplies prior to applying an external reference (where applicable). apply the analog inputs last. when powering up the ad7960 device, first apply 1.8 v (vdd2, vio) to the device, then ramp 5 v (vdd1). set the reference confi guration pins, en0, en1 , and en2, to the correc t values. when an in ternal reference buffer is used (governed by the en1 and en0 values), apply the external reference of 2. 048 v to the refin pin or 5 v/4.096 v to the ref pin. figure 34 . adc core power dissipation vs. throughput, self clocked mode, cnv i n cmos mode , internal reference buffer disabled 40 50 60 70 80 90 100 1 10 100 1k 10k 100k 1m psrr (db) frequenc y (hz) vdd2 = 1.8v vio = 1.8v vdd1 = 5v 09659-124 0 5 10 15 20 25 30 35 40 45 0 1 2 3 4 5 power dissipation (mw) throughput (mhz) 09659-128
data sheet ad7960 rev. 0 | page 19 of 24 digital interface conversion control all analog-to-digital conversions are controlled by the cnv signal. this signal can be applied in the form of a cnv+/cnv? lvds signal, or it can be applied in the form of a 1.8 v cmos logic signal to the cnv+ pin when cnv? is grounded. the conversion is initiated by the rising edge of the cnv signal. after the ad7960 is powered up, the first conversion result generated is valid. the key beneficial feature of the ad7960 is that the user can return to the acquisition phase before the end of the conversion. the two methods for acquiring the digital data output of the ad7960 via the lvds interface are described in the echoed clock interface mode and self clocked mode sections. echoed clock interface mode the digital operation of the ad7960 in echoed clock interface mode is shown in figure 35. this interface mode, requiring only a shift register on the digital host, can be used with many digital hosts (such as fpga, shift register, and microprocessor). it requires three lvds pairs (d, clk, and dco) between each ad7960 and the digital host. the clock dco is a buffered copy of clk and is synchronous to the data, d, which is updated on the falling edge of dco (t d ). by maintaining good propagation delay matching between d and dco through the board and the digital host, dco can be used to latch d with good timing margin for the shift register. conversions are initiated by a rising edge of the cnv pulse. the cnv pulse must be returned low (t cnvh maximum) for valid operation. after a conversion begins, it continues until completion. additional cnv pulses are ignored during the conversion phase. after t msb elapses, the host begins to burst the clk. note that t msb is the maximum time for the msb of the new conversion result. use t msb as the gating device for clk. the echoed clock, dco, and the data, d, are driven in phase with d being updated on the falling edge of dco; the host uses the rising edge of dco to capture d. the only require- ment is that the 18 clk pulses finish before t clkl of the next conversion phase elapses, or the data is lost. after all 18 bits are read, up to t msb , d and dco are driven to 0. set clk to idle low between clk bursts. figure 35. echoed clock interface mode timing diagram clk+ t cyc t acq 18 17 cnv+ 11 8 17 21 2 3 t cnvh t clkl dco+ 18 17 1 1817 2 1 23 d+ sample n s a mple n + 1 d? d1 7 n d1 6 n d1 n clk? cnv? dco? d0 n ? 1 acquisition acquisition t dco t d t clk 0 t msb d1 n ? 1 d17 n + 1 d16 n + 1 d0 n 0 d15 n + 1 t clkd acquisition 09659-018
ad7960 data sheet rev. 0 | page 20 of 24 self clocked mode the digital operation of the ad7960 in self clocked interface mode is shown in figure 36 . this interface mode reduces the number of traces between the adc and the digital host to two lvds pairs (clk and d) or to a single pair if sharing a common clk. multiple ad7960 devices can share a common clk signal. this can be useful in reducing the number of lvds connections to the digital host. when the sel f clocked interface mode is used, each adc data - word is preceded by a 010 header sequence. after t msb has elapsed, t he first bit of the h eader , 0, automatically appears on d , and t he remaining two bit s of the h eader , 10, are then clocked out by the first two clk falling edges at the beginning of the next sample . this header (010) is used to synchronize d of each conversion in the digital host because, in this mode, there is no clock output synchronous to the data (d) to al low the digital host to acquire the data output. synchronization of the d data to the acquisition clock of the digital host is accomplished by using one state machine per ad7960 device. for example, using a state machine that runs at the same speed as clk incorporates three phases of this clock frequency (120 apart). each phase acquires the d data as output by the adc. the ad7960 data captured on each phase of the state machine clock is then compared. the location of the 1 in the header in each set of acquired data allows the user to choose the state machine clock phase that occurs during the data valid window of d. the self clocked mode data capture method allows the digital host to adapt its result capture timing to accommodate varia - tions in propagation delay through any ad7960 , f or example, where data is captured from multiple ad7960 devices sharing a common input clock. conversions are initiated by a cnv pulse. the cnv pulse must be returned low (t cnvh maximum) for valid operation. after a conversion begins, it continues until completion. additional cnv pulses are ignored during the conversion phase. after the time, t msb , elapses, the host begins to burst the clk signal to the ad7960 . all 20 clk pulses must be applied in the window of time framed by t msb and the subsequent t clkl . the required 20 clk pulses must finish before t clkl (referenced to the next conversion phase) elapses. otherwise, the data is lost because it is overwritten by the next conversion result. set clk to idle high between bursts of 20 clk pulses. the header bit and conversion data of the next adc result are output on subseq uent falling edges of clk during the next burst of the clk signal. when the self clocked interface mode is used, the ad7960 also allows the user to p rovide an extra (21 st ) clock pulse to see a guaran teed 0 state at the end of the frame , as shown in figure 37. after t msb has elapsed, the first bit of the h eader sequence, 0, automatically appears on d and the remaining two bits of the h eader , 10, are then clocked out by the first two clk falling edges at the beginning of the next sample. this header (010) is used to synchronize d of each conversion in the digital host because, in this mode, there is no clock output synchronous to the data (d) to allow the digital host to acquire the data output. figure 36 . self clocked interface mode timing diagram 09659-019 clk+ 2019 1 4 2 1 2 3 t acq d+ d? clk? d0 n ? 1 d1 n ? 1 acquisition acquisition t clkd t clk t msb 2019 3 d17 n d16 n d1 n 0 0 1 d0 n d17 n + 1 0 0 1 t cyc cn v+ t cnvh sample n sample n + 1 c nv? acquisition t clkl
data sheet ad7960 rev. 0 | page 21 of 24 figure 37 . self clocked interface mode with extra clock pulse timing diagram clk+ 20 19 21 1 4 2 1 2 3 t acq d+ d? clk? d0 n ? 1 d1 n ? 1 acquisition acquisition t clkd t clk t msb 20 21 19 3 d17 n d16 n d1 n 0 0 1 d0 n d17 n + 1 0 0 1 t cyc cn v+ t cnvh sample n sample n + 1 c nv? acquisition t clkl 09659-020
ad7960 data sheet rev. 0 | page 22 of 24 application s information l ayout design t he printed circuit board that houses the ad7960 so that the analog and digital sections are s eparated and confined to certain areas of the board. avoid running digital lines under the device because these couple noise onto the d evice unless a ground plane under the ad7960 is used as a shield. do not run f ast switching signals, such as cnv or clk , near ana log signal paths. avoid crossover of digital and analog signals . use a t least one ground plane. it can be common or split between the digital and analog sections. in the latter case, join the planes underneath the ad7960 device s. the ad7960 voltage reference input pin , r e f, has dynamic input impedance . decouple ref with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to and, ideally , right up against the ref and ref_gnd pins and connecting them with wide, low impedance traces. finally, decouple the vdd 1, vdd2 , and vio power supplies of the ad7960 with cerami c capacitors, typically 100 nf, placed close to the ad7960 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. e valuating ad7960 performance other recommended guidelines for the ad7960 schematic and layout are outlined in the user guide of the e va l - ad7960fmcz board ( ug - 490) . the fully assembled and tested evaluati on board, user guide , and software for controlling the e va l - ad7960fmcz board from a pc via the e va l - sdp - ch1z are available from the analog devices website at www.analog.com .
data sheet ad7960 rev. 0 | page 23 of 24 outline dimensions figure 38 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body , very very thin quad (cp - 32 - 7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad7960bcpz ?40c to +85c 32 - lead lead frame chip scale package [lfcsp_wq] cp -32 -7 ad7960bcpz -rl7 ?40c to +85c 32 - lead lead frame chip scale package [lfcsp_wq] cp -32 -7 eval - ad7960fmcz evaluation board 1 z = rohs compliant part. compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic at or 32 9 16 17 24 25 8 exposed pa d pin 1 indic at or 3.25 3.10 sq 2.95 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min
ad7960 data sheet rev. 0 | page 24 of 24 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09659 -0- 8/13(0)

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